VHDL / PlanAhead错误：由于没有绑定实体,因此仍然是黑盒子

2019年8月4日 159次阅读

如何解决这个错误？ PlanAhead 14.7能够合成但不能正确模拟这个简单的计数器.实例“dut：countr port map”在sources选项卡中保留红色问号.我已经确保所有信号都被正确实例化;尝试重新添加源;尝试创建一个新项目.使用IP核可能会明显产生这个问题,但我不认为我是.

设计来源：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity countr is
Port (clk : in std_logic;
      reset : in std_logic;
      output: out std_logic_vector(4 downto 0)
 );
end countr;

architecture Behavioral of countr is
signal count : std_logic_vector(4 downto 0);
BEGIN

proc_1: process(clk, reset)
begin
    if reset = '1' then
        count <= (others => '0');
    elsif rising_edge(clk) then
        count <= std_logic_vector(unsigned(count) + 1);
    end if;
end process;
output <= count;
END Behavioral;

模拟来源：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cntr_TB is end cntr_TB;
architecture Behavioral of cntr_TB is
component countr is
port(clk  : in std_logic;
    reset : in std_logic;
    output: out std_logic_vector(4 downto 0)
 );
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal output : std_logic_vector(4 downto 0) := "00000";
signal endOfSim : boolean := false;      
constant period : time := 20 ns;
BEGIN
dut: countr port map (clk => clk, reset => reset, output => output);
clkStimulus: process(clk)
begin
    if endOfSim = false then
        clk <= not clk after period/2;
    end if;
end process;
stim: process
begin
wait for 40 ns;
reset <= '0';
wait;
end process;
END Behavioral;

最佳答案 我删除并重新添加了设计&模拟源,仍然留下黑盒子.我打开了一个新项目,并在项目创建之前添加了源代码,并且模拟运行没有问题.

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