library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;–导入程序中用到的库
entity readout is
port(
clk,rst_n:in std_logic;
clk100M:in std_logic;
ack,dck:in std_logic;
s1,s2,s3,s4,i1,i2,i3,i4,r1,r2,r3,r:out std_logic–实体部分,并定义好输入输出
);
end readout;
architecture one of readout is
signal cnt:std_logic_vector(15 downto 0);
type states is(read_line,read_idel,integretion);–声明三个状态类型,有多少个状态就声明几个状态类型
signal ack1:std_logic;
signal dck1:std_logic;
signal s1_read,s2_read,s3_read,s4_read,i1_read,i2_read,i3_read,i4_read:std_logic;
signal r1_read,r2_read,r3_read,r_read:std_logic;
signal pr_state,nx_state:states;–定义pr_state,nx_state状态属于states类型,一般是定义当前状态prsent_state与下一个状态next_state
component pixel_read is
port (
clk,pixel_up:in std_logic;—100MHZ,10ns
s1,s2,s3,s4,r1,r2,r3,r:out std_logic;
pixel_done:out std_logic
);
end component;//嵌入例化模块 pixel_read
begin
u5:pixel_read port map (
clk=>clk100M,
pixel_up=>ack1,
s1=>s1_read,
s2=>s2_read,
s3=>s3_read,
s4=>s4_read,
r1=>r1_read,
r2=>r2_read,
r3=>r3_read,
pixel_done=>dck1
);
process(clk)
begin
if ack=’0′ then
cnt<=(others=>’0′);
else if rising_edge(clk)then
cnt<=cnt+’1′;
end if;
end if;
end process;
process(cnt)
begin
if cnt<16 then
ack1<=’1′;
else
ack1<=’0′;
end if;
end process;
process (nx_state,clk)
————状态机第一段,状态初始化
begin
if (rst_n=’0′) then
pr_state<=integretion;
elsif rising_edge(clk)then
pr_state<=nx_state;
end if;
end process;
process(pr_state,nx_state,ack,dck)
————状态机第二段,各个状态之间的转移
begin
case pr_state is
when integretion =>
if(ack1=’1′)then
nx_state<=read_line;
else
nx_state<=integretion;
end if;
when read_line =>
if(dck=’1′)then
nx_state<=read_idel;
else
nx_state<=read_line;
end if;
when read_idel=>
nx_state<=integretion;
end case;
end process;
process(pr_state)
————状态机第三段,各个状态输出
begin
case pr_state is
when integretion =>
s1<=’1′;
s2<=’1′;
s3<=’1′;
s4<=’1′;
i1<=’1′;
i2<=’1′;
i3<=’1′;
i4<=’1′;
r1<=’1′;
r2<=’1′;
r3<=’1′;
r<=’1′;
when read_line =>
s1<=s1_read;
s2<=s2_read;
s3<=s3_read;
s4<=s4_read;
i1<=’0′;
i2<=’0′;
i3<=’0′;
i4<=’0′;
r1<=r1_read;
r2<=r2_read;
r3<=r3_read;
r<=r_read;
when read_idel =>
s1<=’0′;
s2<=’0′;
s3<=’1′;
s4<=’0′;
i1<=’0′;
i2<=’1′;
i3<=’0′;
i4<=’0′;
r1<=’1′;
r2<=’0′;
r3<=’0′;
r<=’0′;
end case;
end process;
end one;