vhdl – 如何从综合报告中推断出来

我用xilinx用VHDL编写了80c51架构.为了提高时钟频率,我已将所有80c51指令流水线化.指令能够根据需要执行,例如.当第一条指令被处理时,第二条指令被取出.

但是,尽管从综合报告中创建了3的流水线深度,但我只获得稍高的时钟频率(大约/ -10Hz).我发现瓶颈是由于综合报告指定的一个操作,但我无法理解综合报告.

请问从’SEQ / decode_3到SEQ / i_ram_addr_7’的数据路径是什么?
(从我的猜测,我推断出使用一个案例,当声明检查100相关操作码但不确定这是否是瓶颈.但我无能为力)

因此,我只有2个查询:

首先,流水线操作是否可能不会增加时钟频率,而测试平台是解释时序减少的唯一方法?

其次,我怎样才能推断出我的代码中哪条路径是’SEQ / decode_3到SEQ / i_ram_addr_7’的瓶颈.

感谢任何能帮助解释我的疑惑的人!

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 12.542ns (Maximum Frequency: 79.730MHz)
   Minimum input arrival time before clock: 10.501ns
   Maximum output required time after clock: 5.698ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 12.542ns (frequency: 79.730MHz)
  Total number of paths / destination ports: 113114 / 2670
-------------------------------------------------------------------------
Delay:               12.542ns (Levels of Logic = 10)
  Source:            SEQ/decode_3 (FF)
  Destination:       SEQ/i_ram_addr_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: SEQ/decode_3 to SEQ/i_ram_addr_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q            102   0.591   1.364  SEQ/decode_3 (SEQ/decode_3)
     LUT4_D:I1->O         10   0.643   0.885  SEQ/de_state_cmp_eq002111 (N314)
     LUT4:I3->O            7   0.648   0.740  SEQ/de_state_cmp_eq00711 (SEQ/de_state_cmp_eq0071)
     LUT4:I2->O            3   0.648   0.534  SEQ/i_ram_addr_mux0000<0>11111 (N2301)
     LUT4:I3->O            1   0.648   0.000  SEQ/i_ram_addr_mux0000<0>11270_SW0_SW0_F (N1284)
     MUXF5:I0->O           1   0.276   0.423  SEQ/i_ram_addr_mux0000<0>11270_SW0_SW0 (N955)
     LUT4_D:I3->O          6   0.648   0.701  SEQ/i_ram_addr_mux0000<0>11270 (SEQ/i_ram_addr_mux0000<0>11270)
     LUT3_L:I2->LO         1   0.648   0.103  SEQ/i_ram_addr_mux0000<7>221_SW2_SW0 (N1208)
     LUT4:I3->O            1   0.648   0.423  SEQ/i_ram_addr_mux0000<7>351_SW1 (N1085)
     LUT4:I3->O            1   0.648   0.423  SEQ/i_ram_addr_mux0000<7>2 (SEQ/i_ram_addr_mux0000<7>2)
     LUT4:I3->O            1   0.648   0.000  SEQ/i_ram_addr_mux0000<7>167 (SEQ/i_ram_addr_mux0000<7>)
     FDE:D                     0.252          SEQ/i_ram_addr_7
    ----------------------------------------
    Total                     12.542ns (6.946ns logic, 5.596ns route)
                                       (55.4% logic, 44.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 154 / 154
-------------------------------------------------------------------------
Offset:              8.946ns (Levels of Logic = 6)
  Source:            rst (PAD)
  Destination:       SEQ/i_ram_diByte_1 (FF)
  Destination Clock: clk rising

  Data Path: rst to SEQ/i_ram_diByte_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           444   0.849   1.392  rst_IBUF (REG/ext_int/fd_out1_0__or0000)
     BUF:I->O            445   0.648   1.425  rst_IBUF_1 (rst_IBUF_1)
     LUT3:I2->O            4   0.648   0.730  ROM/data<1>1 (i_rom_data<1>)
     LUT4:I0->O            1   0.648   0.500  SEQ/i_ram_diByte_mux0000<1>17_SW0 (N1262)
     LUT4:I1->O            1   0.643   0.563  SEQ/i_ram_diByte_mux0000<1>32 (SEQ/i_ram_diByte_mux0000<1>32)
     LUT4:I0->O            1   0.648   0.000  SEQ/i_ram_diByte_mux0000<1>60 (SEQ/i_ram_diByte_mux0000<1>)
     FDE:D                     0.252          SEQ/i_ram_diByte_1
    ----------------------------------------
    Total                      8.946ns (4.336ns logic, 4.610ns route)
                                       (48.5% logic, 51.5% route)

=========================================================================

为了让我更具说明性,我将在1个操作码的解码阶段给出一个示例代码的信息.

当解码作为mov指令的opdcode时,以下是这种情况.大约有100个操作码(100个指令),这意味着这个case语句有超过100个语句.

case OPCODE is

–MOV A, Rn
when “11101000” | “11101001” | “11101010” | “11101011” | “11101100” | “11101101” |
“11101110” | “11101111” => case de_state is
when E7 =>

06001

我希望你能更好地了解我的vhdl代码.我将不胜感激任何形式的帮助.谢谢!

最佳答案 既然您正在使用Xilinx,我认为您还可以访问PlanAhead吗?尝试“分析时序/平面布置设计(PlanAhead)”(在“实施设计” – >“放置和路线”下).

PlanAhead应该打开,并在底部为您提供时间结果的视图.选择关键路径(具有最小松弛的路径),右键单击它并选择“原理图”,这将显示所涉及原语的图形视图.然后,您可以右键单击基元并选择“Expand Cone” – > “To Flops”也可以查看周围的组件.

这可以帮助您更好地了解所涉及的信号.尝试将输入和输出信号跟踪到VHDL代码,并专注于该路径以进行优化.

点赞